As electronic processors advance in processing capability, the need for high speed adders which add very large bit size operands directly increases. Unfortunately, conventional adders which have been used in eight and sixteen bit applications become unacceptably slow for thirty-two, sixty-four and higher bit applications. For example, carry select adders such as the adder taught by Bedrij in U.S. Pat. No. 3,100,835 entitled "Selecting Adder" have ranked ordered adders which typically receive carry inputs from each previous bit stage to select a proper carry bit. Therefore, if a large number of bits are implemented, the number of inputs required for the higher order sections which is known as "fan-in" is tremendously large and impractical. The same type of fan-in problem also exists for conventional carry look-ahead adders.